Custom Layout Engineer (Graduate)

THE COMPANY

Established in early 2024, at Analogue Insight we are bridging the Analogue and Digital Worlds for Tomorrow through our Chiplet Solutions. Our core expertise lies in developing cutting-edge Chiplet technology that serves as the building block for advanced communication systems. Our Chiplets are designed to offer high performance, scalability, and integration flexibility, enabling our clients to achieve breakthroughs in computation speed, data processing, and connectivity. For more information about us, check out our website (Analogue Insight) and LinkedIn Page (Analogue Insight™: Overview | LinkedIn).

THE ROLE

We are seeking a motivated Graduate Custom Layout Engineer to join our layout team and help deliver high-quality analog and mixed-signal IP for our chiplet-based solutions, including high-speed SerDes, UCIe die-to-die PHYs and ADC/DAC blocks. Working alongside senior layout engineers and analog designers, you will learn to take blocks from floorplan through verification to tape-out on advanced FinFET technology nodes. This role is well suited to recent graduates who are fascinated by how circuits become silicon, enjoy detailed hands-on work, and want to grow quickly in a fast-moving, high-impact environment.

Hiring Manager:Christian Borelli, Founder and CSO.

KEY RESPONSIBILITIES

• Analog & AMS Block Layout: Implement layout for analog and mixed-signal building blocks (e.g. current mirrors, differential pairs, bias circuits, comparators, passive structures) under the guidance of senior layout engineers.

• Advanced Node Layout: Learn and apply FinFET layout rules and practices on advanced technology nodes, including matching, symmetry, guard rings, well proximity and layout-dependent effects.

• Verification & Sign-off Support: Run DRC, LVS and parasitic extraction, and debug and fix issues efficiently. Build exposure to EMIR, ESD/LUP and PERC checks as you progress.

• Collaboration with Design Teams: Work closely with analog designers to understand circuit intent, sensitive nets and constraints, and translate them into robust physical implementations.

• Scripting & Automation: Learn and use scripting (e.g. SKILL, TCL or Python) to automate repetitive tasks and improve layout productivity and consistency.

• Documentation & Reviews: Document layout decisions and verification status, and take part in layout reviews to learn and share best practice.

WHAT WE’RE LOOKING FOR

Must-have Technical skills:

• Bachelor's or Master's degree in Electrical/Electronic Engineering, Microelectronics or a related field (recent graduates and those graduating within the next 6 months are welcome)

• 0–2 years of experience in IC layout, including internships, placements or university projects

• Solid understanding of CMOS device physics, semiconductor fabrication basics and analog circuit fundamentals

• Awareness of key analog layout concepts such as matching, symmetry, parasitics, electromigration and latch-up

• Hands-on exposure to a layout environment such as Cadence Virtuoso or Synopsys Custom Compiler (coursework or projects count)

• Basic familiarity with physical verification (DRC/LVS), ideally with Pegasus

**Nice-to-have:

**

• Internship or project experience on a FinFET or other advanced-node technology (TSMC, Samsung, GlobalFoundries)

• A completed tape-out from a university, MPW or internship project

• Basic scripting experience (SKILL, TCL, Python or shell)

• Comfort working in a Linux environment

Soft & Professional Skills:

• Clear, structured communication in professional English—able to explain your work concisely

• Collaborative and feedback-oriented mindset, open to learning from reviews

• Strong attention to detail and pride in high-quality work

• Ownership, reliability, and follow-through on commi...